Similar resources¶

VLSI-EDA/PoC¶

PoC has a large collection of constraint files for Xilinx ISE/Vivado and Intel/Altera’s Quartus-II. The initial commit of this repository imported most of the content from VLSI-EDA/PoC: ucf/.

INTI-CMNB-FPGA/fpga_lib¶

fpga_lib contains some YAML files that use a custom format: INTI-CMNB-FPGA/fpga_lib: boards/. A Python script (boardfiles.py) allows generating UCF files from the YAML sources.

ghdl/ghdl-yosys-plugin¶

Constraints files (.pcf and .lpf) for open source boards are based on resources from ghdl/ghdl-yosys-plugin, antonblanchard/ghdl-yosys-blink, im-tomu/fomu-workshop, etc.

litex-hub/litex-boards¶

litex-boards is equivalent to this repository, but constraints are defined as Python modules. It’d be interesting to allow conversions between the YAML and LiteX board definitions. At the same time, from LiteX definitions it should be possible to generate vendor constraint files matching the guidelines.

amaranth-lang/amaranth-boards¶

amaranth-lang/amaranth-boards provides board and connector definition files for Amaranth HDL. It is also equivalent to this repository, but constraints are defined as Python modules. As with litex-boards, it’d be interesting to allow conversions between the YAML and Amaranth HDL board definitions. The syntax used in amaranth-boards feels more streamlined.

SymbiFlow/yosys-symbiflow-plugins¶

yosys-symbiflow-plugins contains plugins for Yosys developed as part of the SymbiFlow project. Some of those plugins are the xdc-plugin or the sdc-plugin. Those take the constraints and information and converts them to annotations on RTL. Annotations can also be directly provided in HDL too. Hence, the aim is to collect everything into the RTL and then write the data back for downstream tools to use. The main benefit of this approach is using the names in RTL, instead of dealing with mangled names after optimisation. See also XDC commands supported by SymbiFlow Yosys Plugins and Yosys and Constraints System.

olofk/fusesoc¶

fusesoc proposes an open source YAML format for defining cores. Hence, the constrains provided in this repository are expected to be used in those core definition sources. Ideally, fusesoc might import the YAML definition, instead of defining different filesets for each tool.

Xilinx/XilinxBoardStore¶

The board data files used with Xilinx Vivado are hosted at Xilinx/XilinxBoardStore. The upstream of Xilinx/XilinxBoardStore: boards/Digilent/ is Digilent/vivado-boards.