Amaranth HDL (previously known as nMigen)
A modern hardware definition language and toolchain based on Python
Chisel/FIRRTL Hardware Compiler Framework
A hardware design language that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs
Coroutine Co-simulation Test Bench (cocotb)
A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Electronic Design Automation Abstraction (EDA²)
Conceptual model for characterising the abstraction layers in Electronic Design Automation (EDA) projects based on Hardware Description Languages (HDLs)
gdsfactory
An open source platform for end to-end photonic chip design and validation
migen
A Python toolbox for building complex digital hardware
MyHDL
Python as a hardware description and verification language
nMigen
A refreshed Python toolbox for building complex digital hardware
PipelineC
Open source C-like hardware description language with high-level-synthesis-like automatic pipelining and several other real life design inspired features.
PyXHDL - Python Frontend For VHDL And Verilog
Use the power of the Python ecosystem to model hardware and generate directly SystemVerilog (>= 2012) and VHDL (>= 2008) source code.
Silice
Silice is an open source language that simplifies writing algorithms fully exploiting FPGA architectures
SpinalHDL
Scala based HDL
SVUnit
SVUnit is an open-source test framework for ASIC and FPGA developers writing Verilog/SystemVerilog code.
Universal VHDL Verification Methodology (UVVM)
description
Verilog to Routing (VTR)
Open Source CAD Flow for FPGA Research
VUnit
Open source unit testing framework for VHDL/SystemVerilog
