Open Source VHDL Verification Methodology (OSVVM)

description

Maintained by: Jim Lewis

Licensed under: Apache-2.0

Open Source VHDL Verification Methodology (OSVVM)

“OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA or ASIC verification project from start to finish. Using these libraries you can create a simple, readable, and powerful testbench that is suitable for either a simple FPGA block or a complex ASIC."

“OSVVM is developed by the same VHDL experts who have helped develop VHDL standards. We have used our expert VHDL skills to create advanced verification capabilities that:

  • Are simple to use and work like built-in language features.

  • Maximize reuse and reduce project schedule.

  • Facilitate readabilty and reviewability by the whole team including software and system engineers.

  • Facilitate debug with HTML based test suite and test case reporting.

  • Provide continuous integration (CI/CD) support with JUnit XML test suite reporting.

  • Provide buzz word features including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering.

  • Rival the verification capabilities of SystemVerilog + UVM."

  • Verification IPs:

  • Written In: VHDL

  • Supports: Constrained Random Test Generation, Functional Coverage Collection, and more