Tools

edalize
An abstraction library for interfacing EDA tools

fusesoc
Package manager and build abstraction tool for FPGA/ASIC development

GHDL
Open-source analyzer, compiler, simulator and synthesizer for VHDL

HDLmake
A tool designed to help FPGA designers to manage and share their HDL code by automatically finding file dependencies, writing synthesis & simulation Makefiles, and fetching IP-Core libraries from remote repositories

pyFPGA
A Python package to use FPGA development tools programmatically

pyIPCMI
A Python-based IP Core Management Infrastructure

RgGen
Code generator for configuration and status registers

verilator
Open-source compiler/simulator for syntehsizable Verilog or SystemVerilog

Versatile Place and Route (VPR)
Open source academic CAD tool designed for the exploration of new FPGA architectures and CAD algorithms, at the packing, placement and routing phases of the CAD flow