Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the vvp command. For synthesis, the compiler generates netlists in the desired format.
Icarus Verilog (iverilog)
Verilog simulation and synthesis tool
Maintained by: Stephen Williams
Licensed under: GPL-2.0-or-later
