verilog

Chisel/FIRRTL Hardware Compiler Framework
A hardware design language that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs

Coroutine Co-simulation Test Bench (cocotb)
A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

edalize
An abstraction library for interfacing EDA tools

Electronic Design Automation Abstraction (EDA²)
Conceptual model for characterising the abstraction layers in Electronic Design Automation (EDA) projects based on Hardware Description Languages (HDLs)

fusesoc
Package manager and build abstraction tool for FPGA/ASIC development

Icarus Verilog (iverilog)
Verilog simulation and synthesis tool

LibreCores
Your gateway to free and open source digital designs and other components that you can use and re-use in your digital designs

OpenCores
Online community for the development of gateware IP Cores

pyFPGA
A Python package to use FPGA development tools programmatically

RgGen
Code generator for configuration and status registers

Silice
Silice is an open source language that simplifies writing algorithms fully exploiting FPGA architectures

SpinalHDL
Scala based HDL

SVUnit
SVUnit is an open-source test framework for ASIC and FPGA developers writing Verilog/SystemVerilog code.

Synthesijer
A compiler from Java to VHDL/Verilog-HDL

verilator
Open-source compiler/simulator for syntehsizable Verilog or SystemVerilog

Verilog to Routing (VTR)
Open Source CAD Flow for FPGA Research