“OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA or ASIC verification project from start to finish. Using these libraries you can create a simple, readable, and powerful testbench that is suitable for either a simple FPGA block or a complex ASIC."
“OSVVM is developed by the same VHDL experts who have helped develop VHDL standards. We have used our expert VHDL skills to create advanced verification capabilities that:
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Are simple to use and work like built-in language features.
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Maximize reuse and reduce project schedule.
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Facilitate readabilty and reviewability by the whole team including software and system engineers.
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Facilitate debug with HTML based test suite and test case reporting.
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Provide continuous integration (CI/CD) support with JUnit XML test suite reporting.
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Provide buzz word features including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering.
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Rival the verification capabilities of SystemVerilog + UVM."
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Verification IPs:
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Written In: VHDL
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Supports: Constrained Random Test Generation, Functional Coverage Collection, and more