Coroutine Co-simulation Test Bench (cocotb)
A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Electronic Design Automation Abstraction (EDA²)
Conceptual model for characterising the abstraction layers in Electronic Design Automation (EDA) projects based on Hardware Description Languages (HDLs)
gdsfactory
An open source platform for end to-end photonic chip design and validation
MyHDL
Python as a hardware description and verification language
Pono
An SMT-based model checker built on smt-switch.
SVUnit
SVUnit is an open-source test framework for ASIC and FPGA developers writing Verilog/SystemVerilog code.
SymbiYosys (sby)
Front-end driver program for Yosys-based formal hardware verification flows
Universal VHDL Verification Methodology (UVVM)
description
VUnit
Open source unit testing framework for VHDL/SystemVerilog
