pyVHDLParser
A token-stream based parser for VHDL-2008 creating a document object model (DOM).
Coroutine Co-simulation Test Bench (cocotb)
A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
eda-twiki
Wiki of the VHDL Analysis and Standardization Group (VASG)
edalize
An abstraction library for interfacing EDA tools
Electronic Design Automation Abstraction (EDA²)
Conceptual model for characterising the abstraction layers in Electronic Design Automation (EDA) projects based on Hardware Description Languages (HDLs)
fphdl
VHDL-2008 Support Library
fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
GHDL
Open-source analyzer, compiler, simulator and synthesizer for VHDL
ghdl-yosys-plugin
Plugin for using GHDL as a VHDL frontend for Yosys
hdlConvertor
System Verilog and VHDL parser, preprocessor and code generator for Python/C++ written
JSON-for-VHDL
A JSON library implemented in VHDL
LibreCores
Your gateway to free and open source digital designs and other components that you can use and re-use in your digital designs
NVC
A GPLv3 VHDL compiler and simulator aiming for IEEE 1076-2002 compliance
OpenCores
Online community for the development of gateware IP Cores
Pile of Cores Library (PoC)
A library of free, open-source and platform independent IP cores
PipelineC
Open source C-like hardware description language with high-level-synthesis-like automatic pipelining and several other real life design inspired features.
pyFPGA
A Python package to use FPGA development tools programmatically
pyVHDLModel
An abstract language model of VHDL written in Python
rust_hdl
Collection of HDL related tools
SpinalHDL
Scala based HDL
Synthesijer
A compiler from Java to VHDL/Verilog-HDL
tsfpga
Tools for managing modern FPGA project
Universal VHDL Verification Methodology (UVVM)
description
VASG Packages
Open source materials referenced by the IEEE 1076 standard
VHDL-extras
Bits of code that are not found in the standard VHDL libraries
VUnit
Open source unit testing framework for VHDL/SystemVerilog
