Verilog to Routing (VTR)

“The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture."

It performs:

• Elaboration & Synthesis (ODIN II)
• Logic Optimization & Technology Mapping (ABC)
• Packing, Placement, Routing & Timing Analysis (VPR)

“to generate FPGA speed and area results. […] VTR can also produce FASM to program some commercial FPGAs (via Symbiflow)."

References:

• Yosys
• Versatile Place and Route
• SymbiFlow
• FASM