Axion-HDL

AXI4-Lite register interface generator from HDL annotations or structured data files

Maintained by: Bugra Tufan

Licensed under: MIT

Axion-HDL generates AXI4-Lite register interfaces from inline HDL annotations or standalone data files (YAML, TOML, XML, JSON). Registers are described directly inside VHDL or SystemVerilog source files using @axion comments, removing the need for a separate register description language.

Axion-HDL can:

  • Read register definitions from inline @axion comments in VHDL or SystemVerilog source files
  • Read standalone register map files in YAML, TOML, XML, or JSON format
  • Generate synthesizable VHDL and SystemVerilog AXI4-Lite register block modules
  • Generate C headers with access macros for software integration
  • Generate HTML register map documentation
  • Export register maps back to YAML, TOML, XML, or JSON
  • Insert built-in clock domain crossing (CDC) synchronizers, configurable per module
  • Pack multiple fields into a single address (subregisters) and auto-split wide signals across addresses