Coroutine Co-simulation Test Bench (cocotb)
A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Electronic Design Automation Abstraction (EDA²)
Conceptual model for characterising the abstraction layers in Electronic Design Automation (EDA) projects based on Hardware Description Languages (HDLs)
hdlConvertor
System Verilog and VHDL parser, preprocessor and code generator for Python/C++ written
RgGen
Code generator for configuration and status registers
SVUnit
SVUnit is an open-source test framework for ASIC and FPGA developers writing Verilog/SystemVerilog code.
verilator
Open-source compiler/simulator for syntehsizable Verilog or SystemVerilog
VUnit
Open source unit testing framework for VHDL/SystemVerilog
