These images are coloured BROWN in the Graphs.
Multiple tools from fine-grained images are included in larger images for common use cases.
These are named
This is the recommended approach for users who are less familiar with containers and want a quick replacement for
full-featured virtual machines.
Coherently, some common Unix tools (such as make or cmake) are also included in these all-in-one images.
gh:tmeissner/formal_hw_verification: the CI workflow uses image
REGISTRY_PREFIX/[ARCHITECTURE/][COLLECTION/]formal/allalong with GitHub Actions’ Docker Step syntax.
gh:stnolting/neorv32-setups: the implementation workflow (for generating bitstreams from VHDL sources) uses image
REGISTRY_PREFIX/[ARCHITECTURE/][COLLECTION/]implalong with GitHub Actions’ Docker Step syntax.
As explained in F4PGA (Conda), multiple ready-to-use images are provided including Miniconda, F4PGA toolchains and architecture definitions for Xilinx’s xc7 or QuickLogic’s eos-s3 devices. These container images are expected to be used as explained in , assuming that the environment is prepared already and available in the PATH. Hence, the Conda environment can be activated straightaway. See, for instance:
:~# git clone https://github.com/chipsalliance/f4pga-examples ... :~# cd f4pga-examples :~/f4pga-examples# docker run --rm -it \ -v /$(pwd)://wrk \ -w //wrk \ gcr.io/hdl-containers/conda/f4pga/xc7/a100t ... (xc7) root@c3d4dd1d97cc:/wrk# TARGET="arty_100" make -C xc7/picosoc_demo/ ... (xc7) root@c3d4dd1d97cc:/wrk# ls -1 xc7/picosoc_demo/build/arty_100/ constraints.place fasm.log pack.log packing_pin_util.rpt place.log pre_pack.report_timing.setup.rpt report_timing.hold.rpt report_timing.setup.rpt report_unconstrained_timing.hold.rpt report_unconstrained_timing.setup.rpt route.log top.bit top.eblif top.fasm top.ioplace top.json top.json.carry_fixup.json top.json.carry_fixup_out.json top.json.post_abc9.ilang top.json.pre_abc9.ilang top.net top.net.post_routing top.place top.route top.sdc top_io.json top_synth.log top_synth.v top_synth.v.premap.v