All awesome resources

pyVHDLParser
A token-stream based parser for VHDL-2008 creating a document object model (DOM).

Boolector
A Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, arrays and uninterpreted functions

Calyx
Intermediate language and infrastructure for Hardware Accelerator Generators

Cascade
A Just-In-Time Compiler for Verilog

Clash
A modern, functional, hardware description language

Coriolis
Free database, placement tool and routing tool for VLSI design

ecpprog
Programmer for the Lattice ECP5 series, making use of FTDI based adaptors

eda-twiki
Wiki of the VHDL Analysis and Standardization Group (VASG)

edalize
An abstraction library for interfacing EDA tools

FASM
FPGA Assembly (FASM) Parser and Generator

FPGACPU.CA
A resource about FPGAs, computer history, and computer architecture

fphdl
VHDL-2008 Support Library

fritzing
Electronic Design Automation software with a low entry barrier, suited for the needs of makers and hobbyists

fujprog
FPGA JTAG programmer for ULX2/3S boards

fusesoc
Package manager and build abstraction tool for FPGA/ASIC development

gdsfactory
An open source platform for end to-end photonic chip design and validation

GHDL
Open-source analyzer, compiler, simulator and synthesizer for VHDL

Graphviz
Open source graph visualization software

HDL Checker
Repurposing existing HDL tools to help writing better code

hdlConvertor
System Verilog and VHDL parser, preprocessor and code generator for Python/C++ written

HDLmake
A tool designed to help FPGA designers to manage and share their HDL code by automatically finding file dependencies, writing synthesis & simulation Makefiles, and fetching IP-Core libraries from remote repositories

HWToolkit (hwt)
VHDL/Verilog/SystemC code generator and simulator API written in Python/C++

icestorm
Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

Kactus2
A graphical EDA tool based on the IP-XACT standard

KiCad
Cross Platform and Open Source Electronics Design Automation Suite

KLayout
An accurate and fast viewer for big mask layout files

legoHDL
The package manager and development tool for Hardware Description Languages (HDL)

LibreCores
Your gateway to free and open source digital designs and other components that you can use and re-use in your digital designs

LibreCores CI
Continuous Integration of projects being hosted on LibreCores

LiteX
A Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create Cores/SoCs (with or without CPU)

LiveHD
A productive infrastructure for Synthesis and Simulation

Magic
A venerable VLSI layout tool

migen
A Python toolbox for building complex digital hardware

mistral
Cyclone V FPGAs Bitstream Documentation (Reverse Engineered)

MyHDL
Python as a hardware description and verification language

Netgen
Netlist comparison (LVS) and format manipulation

netlistsvg
Draw SVG schematics from a Yosys JSON netlists

nextpnr
A vendor neutral, timing driven, FOSS FPGA place and route tool

ngspice
Mixed-level/Mixed-signal circuit simulator based on Spice3f5, Cider1b1, and Xspice

nMigen
A refreshed Python toolbox for building complex digital hardware

NVC
A GPLv3 VHDL compiler and simulator aiming for IEEE 1076-2002 compliance

Open Source Design Automation (OSDA)
One-day workshop to bring together industrial, academic, and hobbyist actors to explore, disseminate, and network over ongoing efforts for open design automation

OpenCores
Online community for the development of gateware IP Cores

OpenOCD
Free and Open On-Chip Debugging, In-System Programming and Boundary-Scan Testing

OpenROAD
24-hour, No-Human-In-The-Loop layout design for SOC, Package and PCB with no Power-Performance-Area (PPA) loss

OpenSTA
A gate level static timing verifier

ORConf
Annual conference for open source digital, semiconductor and embedded systems designers and users

Pinout
Python package that generates hardware pinout diagrams as SVG images

PipelineC
Open source C-like hardware description language with high-level-synthesis-like automatic pipelining and several other real life design inspired features.

Pono
An SMT-based model checker built on smt-switch.

Project Bureau
Documenting the Microchip (Atmel) ATF15xx CPLD fuse maps and programming algorithms

Project Oxide
Lattice 28nm FPGAs Bitstream Documentation (Reverse Engineered)

Project Trellis
Lattice ECP5 FPGAs Bitstream Documentation (Reverse Engineered)

Project U-Ray
Xilinx Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC Bitstream Documentation (Reverse Engineered)

Project X-Ray
Xilinx Xilinx 7-series FPGAs Bitstream Documentation (Reverse Engineered)

pyFPGA
A Python package to use FPGA development tools programmatically

PyHDI
Python-based Hardware Development Infrastructure

pyIPCMI
A Python-based IP Core Management Infrastructure

pyVHDLModel
An abstract language model of VHDL written in Python

RapidWright
An open source platform from Xilinx Research Labs with a gateway to backend tools in Vivado

renode
An open source software development framework with commercial support from Antmicro that lets you develop, debug and test multi-node device systems reliably, scalably and effectively

RgGen
Code generator for configuration and status registers

scopehal
Oscilloscope / logic analyzer platform abstraction library

sigrok-cli
A portable, cross-platform, Free/Libre/Open-Source signal analysis software suite

Silice
Silice is an open source language that simplifies writing algorithms fully exploiting FPGA architectures

SiliconCompiler
An open source compiler framework that automates translation from source code to silicon

SKiDL
A module that extends Python with the ability to design electronic circuits

SpyDrNet
A flexible framework for analyzing and transforming FPGA netlists

Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler

SVUnit
SVUnit is an open-source test framework for ASIC and FPGA developers writing Verilog/SystemVerilog code.

SymbiFlow
A fully open source flow for the development of FPGAs of multiple vendors

Torc
Tools for Open Reconfigurable Computing

tsfpga
Tools for managing modern FPGA project

VASG Packages
Open source materials referenced by the IEEE 1076 standard

Verible
A suite of SystemVerilog developer tools, including a parser, style-linter, and formatter

verilator
Open-source compiler/simulator for syntehsizable Verilog or SystemVerilog

Versatile Place and Route (VPR)
Open source academic CAD tool designed for the exploration of new FPGA architectures and CAD algorithms, at the packing, placement and routing phases of the CAD flow

VHDL-extras
Bits of code that are not found in the standard VHDL libraries

VUnit
Open source unit testing framework for VHDL/SystemVerilog

wavedrom
Javascript wave graph visualizer for documentations and sim

Xeda
A cross-platform, cross-EDA, cross-target simulation and synthesis automation platform

XLS
Accelerated HW Synthesis

XSCHEM
Schematic capture and netlisting EDA tool

Xyce
An open source, SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms

Yices 2
A solver for Satisfiability Modulo Theories (SMT) problems

Z3
A theorem prover